Examples of the prior art related to a method for processing the layout of logic elements of semiconductor integrated circuits include a technique described in the Japanese Patent Laid-Open Publication No. 8-274177 is known. This example of the prior art provides a method for processing the layout of logic elements to optimize the layout of the logic elements with respect to signal transfer delays in which each logic element of a logic element group, which is logically divided into logic block units, each consisting of logic elements, and logically designed in a hierarchical structure, and is laid out on a semiconductor integrated circuit board, with the logic elements belonging to the same logic block being clustered together in the layout.
According to the example of the prior art described in the aforementioned Japanese Patent Laid-Open Publication No. 7-73643, layout is processed by causing information for optimizing the layout of logic elements with respect to signal transfer delays to be automatically recognized by the connection relationship among the logic elements.
However, this example of the prior art takes into consideration the connection relationship among all the logic elements and, since semiconductor integrated circuits have recently taken on much larger scales, it is anticipated that enormous processing hours will be required if the entire layout is to be processed in this manner, which might prove to be a factor to prevent the layout to be designed in a short period of time.
Yet, since logic elements to be taken account of in addressing signal delays or the like are limited to some specific logic elements, and likewise what governs the operating speed of a semiconductor integrated circuit is the signal transfer time pertaining to connection among specific logic elements, it was found unnecessary to optimize the layout of all the logic elements.
An object of the present invention, therefore, is to provide a method for processing the layout of logic elements of semiconductor integrated circuits capable of enabling the layout design to be accomplished in a short period of time by optimizing the layout of logic elements.